1. Field of the Invention
The present invention relates to the field of electrical rule checking of integrated circuit designs. Specifically, the present invention relates to computer-aided generation of input files for circuit simulators and computer-aided analysis of circuit simulator output for high voltage MOS design rule violations.
2. Discussion of the Related Art
In MOS integrated circuit design, it is necessary to guarantee that certain electrical design rules are never violated. For example, in MOS devices, if the voltage across the gate oxide exceeds the amount which can be handled by the gate oxide, a charge transfer may rupture the gate oxide, causing device failure or unreliability. This is called gate oxide breakdown.
Similarly, if the voltage from the source to drain or drain to source is too large to be carried by the channel of a MOS device, a large current may "punch through" the channel, causing circuit failure and sometimes damaging the device due to excessive heating. This is particularly true at small channel lengths and high voltages. Another type of failure occurs if the source or drain voltage of a MOS device is too high relative to the bulk. Here, the source or drain to bulk junction may breakdown, causing erroneous unintended circuit behavior.
These types of problems can be avoided by formulating and following certain high voltage electrical design rules.
In most low-voltage MOS integrated circuits, the circuit can be designed so that all the transistors will behave properly and will not be damaged under any normal operating circumstances. In other words, the highest specified supply voltages will never cause the any of the internal MOS devices to fail or operate improperly.
However, flash memory devices utilize the internal generation of high voltages which are much higher than the highest supply voltages of the devices. It is difficult to guarantee that these high voltage design rules will never be violated.
Circuit designers frequently use circuit simulators such as SPICE to perfect circuit performance and to attempt to develop circuits which adhere to the electrical design rules. In order to guarantee adherence to the high voltage electrical design rules, it is desirable to be able to detect high voltage design rule violations that have occurred in a simulation. However, the transistor models used in these simulators typically do not model transistor failure or breakdown. Rather, the user must carefully monitor the transistor's circuit nodes to verify that none of the conditions which might cause problems have happened.
However, this is a very difficult tool because the high voltage electrical design rules themselves are non-linear voltage dependent rules which require monitoring voltage differentials between several dynamic nodes for each transistor. In the past circuit designers have relied upon manual checking of simulation reports and visual graphical analysis of simulation reports to try to detect high voltage design rule violations. This manual checking is tedious and very error prone.
As is apparent from the foregoing discussion, a need exists for an automated system for checking a circuit for high voltage design rule violations.